Design of Partially Paralle Scan Chain
نویسندگان
چکیده
This paper presents a design-for-testability technique, called partially parallel scan chain ( PPSC ), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced.
منابع مشابه
An Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain
In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The seeds are obtained by solving systems of l...
متن کاملMultiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
Multiple scan chain has been used in DFT (design for test) architectures primarily to reduce test application time. Since power is an emerging problem, in this paper, we present a design technique for multiple scan chain in BIST (Built-In Self Test) to reduce average power dissipation and test application time, while maintaining the fault coverage. First, we partition the scan chain into a set ...
متن کاملA Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed...
متن کاملVirtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are identical to the I/O pins of a core with a normal scan chain. For the system integrator, testing a core with a virtual scan chain is identical...
متن کاملScan Chain 1 Mux 1 0 Scan Chain 2 Mux 1 0 Scan
We propose a new design for testability technique, Parallel Serial Full Scan (PSFS), for reducing the test application time for full scan embedded cores. Test application time reduction is achieved by dividing the scan chain into multiple partitions and shifting in the same vector to each scan chain through a single scan in input. The experimental results for the ISCAS89 circuits showed that PS...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1997